Dynamic Voltage and Frequency Scaling

With the ever increasing demand for high performance from handheld devices, comes the realization that high performance is not without cost. The cost of high performance is power consumption. At the same time consumers are demanding high performance and long battery life. Traditionally, these things have been at odds and generally speaking a choice had to be made between performance and battery life. Today’s embedded processors are equipped with power saving features that try to save power while at the same time deliver high performance.

One method that is increasingly being used to reduce the power consumption, while maintaining high performance is Dynamic Voltage and Frequency Scaling hereafter referred to as “DVFS.” The key idea behind DVFS is to scale the voltage and frequency of the processor to provide “just-enough” circuit speed to process the system workload while meeting the total compute time and/or throughput constraints, and thereby, reducing the energy dissipation. Since the energy dissipated per cycle with CMOS circuitry scales quadratically to the supply voltage, DVFS can potentially provide significant energy savings. In other words, the power consumed by a processor is proportional to the frequency and to the voltage squared.

Significant research and development efforts on DVFS have been made in the last 10 years. Numerous approaches and algorithms have been researched, proposed, and simulated. There are two basic categories for these algorithms, real-time and non real-time algorithms.

Within the non real-time category, there are many different proposed algorithms. For example, in programs with a high cache miss ratio, performance can be limited by memory bandwidth rather than CPU speed. Since memory performance is not affected by a change in CPU speed, increasing or decreasing the CPU frequency will have little effect on the performance of these programs. Researchers have been trying to exploit this program behavior in order to achieve greater power and reduced energy consumption.

One common approach is to predict execution time and to decompose program workload into regions based on their CPU-boundedness. The decomposition can be done statically using profiling information or through a built-in performance monitoring unit (PMU). While these algorithms show significant benefit, they are simply not appropriate for real-time applications because of the performance loss they produce.

In real-time scenarios, careful attention must be paid to ensure that DVFS solutions do not add latency that violates real-time constraints for task execution. Some solutions that may be appropriate for real-time applications are microarchitecture-driven approaches using voltage scaling during processor idle periods to provide energy savings without performance loss, etc.

Other solutions, at the system level, include CPU idle monitoring and reducing voltage and frequency when the CPU is idle, thereby saving energy and extending battery life.

While DVFS is not a silver-bullet in terms of providing energy savings, it is one of many tools that may be employed to significantly reduce power consumption of hand-held battery devices, thereby extending the use of devices before requiring recharging. And while no single algorithm fits all platforms, DVFS solutions should be part of the design decisions from inception of any product that would benefit from power savings.